Integrated circuits often employ electrostatic discharge protection to prevent damage to electronic devices during an electrostatic discharge event. Such protection may prevent damage from high voltage or current transients, including those that may occur during installation. Metal oxide semiconductor (MOS) integrated circuits are particularly vulnerable to electrostatic discharge because an electrostatic discharge event may melt the silicon or damage gate oxides and/or the short channel devices used in their design. Designing integrated circuits into deep sub-micron scale presents challenges to traditional forms of electrostatic discharge protection.
One prior approach used for electrostatic discharge protection employs a lateral NPN transistor formed by an n-channel MOSFET (NMOS) or field oxide device between the input pad and a substrate closely coupled to ground. The device is used to shunt to ground the large transient current caused by an electrostatic discharge event by turning on the lateral NPN when an event occurs. This approach may also utilize a vertical PNP transistor with a collector common to the substrate to trigger forward biasing of the lateral NPN transistor. When placed near the lateral NPN transistor, the vertical PNP transistor may lower the trigger voltage of the lateral NPN by raising the local substrate potential near the base of the lateral NPN transistor.
This prior approach may not be particularly effective in deep sub-micron products, such as those utilizing silicided CMOS technology. Silicided CMOS products generally have low substrate resistance and often encounter problems with uniform turn-on, and even failure, of the lateral NPN transistor. This approach may also not be particularly advantageous for mixed signal products, where chip capacitance is normally substantially smaller. In such products, large substrate current injection may be desirable to bias the substrate near the lateral NPN transistor. Larger circuit area, not usually available in modern sub-micron designs, may be used to achieve such current injection. Furthermore, the vertical PNP trigger may become de-biased at these chip capacitances. Therefore, a suitably-sized device resistant to de-biasing is needed to provide relatively uniform current injection into the substrate, to activate the lateral NPN transistor.
The invention comprises a system and method for providing electrostatic discharge protection. In one embodiment of the invention, an integrated circuit comprising at least one input element is protected by a protective circuit. The protective circuit is operable to protect the integrated circuit from damage due to electrostatic discharge and may be coupled to the input element. The protective circuit comprises a lateral NPN transistor coupled to the input element and operable to activate when the input element voltage exceeds threshold, the threshold greater than or equal to the ordinary operating voltage of circuitry coupled to the input element. The protective circuit also comprises a lateral PNP transistor coupled to the input element and to the lateral NPN transistor. The lateral PNP transistor is operable to aid in raising a potential of the base of the lateral NPN transistor. Alternatively, the protective circuit also may use a PMOS transistor, or a PMOS transistor in combination with the lateral NPN transistor, coupled to the input element and to the lateral NPN transistor. The PMOS transistor is operable to aid in raising the potential of the base of the lateral NPN transistor.
The invention provides several important technical advantages. The invention is particularly advantageous in providing uniform turn on of the lateral NPN transistor. The protection circuit is not subject to de-biasing at smaller chip capacitances. Thus, the invention may be used for integrated circuits utilizing silicided CMOS, mixed signal products, or other deep sub-micron or smaller technologies. The invention may also be used with larger technologies. The disclosed protection circuit does not require a large design area in order to provide electrostatic discharge protection, thus potentially conserving valuable circuit space.